Figure 1 – (a) Schematic of the electrooptic prober. Electrical signals are supplied to the device with automated testers and electrooptic probing performed with the scanning optical microscope. (b) The layout of a sub-20 nm FinFET device under inspection. The distances between neighboring transistors are (i) 150 nm, (ii) 200 nm and (iii) 80 nm, respectively. (c) Micrograph shows electro-optic frequency mapping. The state-of-art tool’s optical resolution is 135nm but can be seen to resolve better than 80nm electro-optically [1]. (d) Optical Fault Isolation on FinFETs performed with the aid of simulations using a newly developed fault isolation technique between AMD Singapore and SUTD. The simulations match signals from good dies (blue tracers) and mismatch with rejects (red traces), through which individual nanoscale transistor with defects can be isolated for root cause identification.

Introduction

In today’s advanced semiconductor technologies like sub-10nm FinFET, emerging memories like STT-MRAM and emerging new computing architectures like neuromorphic computation, failure analysis and reliability of such devices and circuits are challenging. Conventional approaches using optical means for fault isolation in integrated circuit failure analysis (ICFA) have reached their physical limit in isolating sub-14nm devices effectively for further in-depth failure analysis. Similarly, new methodologies and standards have to be established to provide comprehensive reliability assessment for emerging technologies like spin transfer torque magnetic random access memory (STTMRAM) and neuromorphic computing circuits. As such, new ICFA techniques and reliability assessment methodologies have to be developed to ensure the state of-the-art semiconductor technologies are adequately and appropriately analyzed and qualified in time to meet industrial demands. 

Melting Pot of Expertise 

In addition to our current contribution to the world semiconductor wafer and substrate fabrication and production, equipment manufacturing and packaging, Singapore has been playing a key role in the area of ICFA and reliability over the past 3 decades. Our ICFA and reliability scientists and researchers have contributed significantly to the scientific progress and technological advancements in ICFA and reliability, and have made their presence felt at the global stage. Besides representing their host institutions and companies in Singapore, as chair or members of advisory boards, organizing or technical committee at the world renowned semiconductor reliability / failure analysis related international conferences and meetings such as IEEE IEDM, IRPS, ECTC, ESREF, ISTFA, IPFA, EPTC etc., they have provided a significant imprint in the research and development of ICFA and reliability by contributing to scientific discovery and know-hows by publishing their research outcomes regularly, giving invited talks and conducting tutorials.

As early as 1989, an International Symposium on the Physical and Failure Analysis of Integrated Circuits was started by an interest group of faculty members from NUS and industrial practitioners in Singapore. IPFA conference, organized by the IEEE Singapore EPS/EDS/Rel Chapter, has now evolved to be one of the world top 4 conferences and continues to be the premier semiconductor FA and Reliability conference in this region alternating between Singapore and Asia Pacific (China, Taiwan, India and Korea) which has significant footprint in semiconductor technology advancement. In conjunction with IPFA, a sister conference called Electronics Packaging Technology Conference (EPTC), which is also organized by the IEEE Singapore EPS/EDS/Rel Chapter, focusing on packaging covering key aspects of failure analysis of advanced packaging technologies started in 1997 and has become another anchor meeting in Asia Pacific annually for the packaging community. Both IPFA and EPTC draw in about 500 participants annually, illustrating the important role of Singapore in these critical domain areas of advanced semiconductor technologies.

Talent and Technology Development and “Center for Excellence” 

Despite our small community of ICFA and reliability in Singapore, Singapore is able to contribute significantly to the technology and talent development of ICFA and reliability internationally. Many semiconductor companies including Infineon, Qualcomm, AMD and Xilinx have significant FA Lab presence in Singapore, even though the manufacturing and production are based elsewhere in the region. Through various collaborative platforms like Economic Development Board Singapore sponsored Industrial Postgraduate Program (IPP), semiconductor companies in Singapore have been actively recruiting talent and engaging in state-of-the-art research and development on ICFA and Reliability with universities including SUTD, NUS and NTU. This collaborative approach has generated significant technological intellectual properties for most advanced semiconductor technologies. As a good example in ICFA, an electro optical fault isolation technique has been successfully developed to resolve sub-14nm start-of-the-art devices by correlating the optical probe signal and that of an electrical response. Figure 1 shows one of the developed capabilities between AMD Singapore and SUTD that the electro-optical response profiles of nano-scale FinFET devices are clearly distinguished and resolved for more advanced in-depth analysis. This fault isolation technique is the most advanced of its kind and together with simulated response profiles of the propagated signals, defective devices which are in a few tens of nanometers and are much smaller than the probed wavelength can be “spatially” resolved for root cause identification. Such achievement clearly shows that Singapore has the expertise, capabilities and advanced technologies to stay relevant and forefront at the international stage. 

Another key example from a reliability domain is our recent work focusing on the reliability assessment of STT-MRAM which is a non-volatile data storage device that is poised to replace Flash, PCRAM and possibly RRAM in the near future due to its very high endurance and integration density. STT-MRAM comprises an ultra-thin MgO dielectric, which is about 1 nm thick, and the dielectric breakdown of this layer can cause catastrophic failure of the device and its array as well. Under another EDB sponsored IPP collaboration between SUTD and GlobalFoundries Singapore, a project focusing on examining the 1nm MgO reliability in state-of-the-art STT-MRAM devices under various new operating conditions was developed. Several new findings have been reported recently from this IPP partnership which provided new reliability assessment methodologies for modelling and predicting polarity dependence TDDB and incorporating significant self-heating effect on area scaling in these nanoscale cylindrical devices as shown in Figure 2. Non-standard defect clustering model was formulated and applied to predict and extrapolate the time-to-failure of the STT-MRAM stacks at field use. The key results were presented at the recent IEEE IEDM and IRPS conferences in US and used for technology qualification. This example illustrates another very successful and unique tripartite partnership model among wafer fab industry (GlobalFoundries), government agency (i.e., EDB) and university (SUTD) in Singapore in advancing reliability research in advanced semiconductor technologies. Such tripartite partnership model is hardly seen elsewhere.

Looking Ahead

The aforementioned two examples show that Singapore ICFA and Reliability community is able to provide leadership in technological innovation and development of new ICFA techniques and reliability assessment methodologies to position Singapore as a hub or even a “Center for Excellence”. With further initiatives from the government agency, industry and academia, we should aim to further leverage on such tripartite collaborations to spearhead new innovations in the ICFA and reliability domain by cross fertilization of ideas, enabled through a common efficient exchange of talent and resources through several education / research / training programs. 

REFERENCES

  1. V. K. Ravikumar, G. Lim, J. M. Chin, K. L. Pey, and J. K. W. Yang, “Understanding spatial resolution of laser voltage imaging,” Microelectronic Reliability, vol. 88–90, pp. 255–261, 2018.
  1. J.H. Lim, N. Raghavan, A. Padovani, J. H. Kwon, K. Yamane, H. Yang, V. B. Naik, L. Larcher, K. H. Lee, and K. L. Pey, “Investigating the Statistical-Physical Nature of MgO Dielectric Breakdown in STT-MRAM at Different Operating Conditions.” In 2018 IEEE International Electron Devices Meeting (IEDM), pp. 25-3, 2018.
  1. J.H. Lim, N. Raghavan, V.B. Naik, J.H. Kwon, K. Yamane, H. Yang, K.H. Lee and K.L. Pey, “Correct Extrapolation Model for TDDB of STT-MRAM MgO Magnetic Tunnel Junctions”, In 2019 IEEE International Reliability Physics Symposium (IRPS), pp. 1-7, 2019.