Chip-Package Interaction, Characterization and Challenges for Advanced IC Packaging


IC packaging performance and reliability is intricately dependent on the materials selected.  The choice of the right materials enables a high degree of mechanical protection, chemical immunity, thermal conductivity, and electrical performance.  Alternately, selecting incompatible materials can result in packages that aren’t capable of meeting customer performance or reliability requirements, potentially delaying product introduction and costing large sums of money and credibility for unsuccessful companies.  The interplay between package materials and on-chip reliability, termed “Chip-Package Interaction,” leads to another level of complexity that must be mastered to enable full entitlement of IC technologies and to avoid qualification tragedies.

A successful package development engineer must be well versed in all the materials used within a package and their interplay.  Understanding Chip-Package Interaction , Characterization, and Challenges for Advanced IC Packaging builds skills covering the fundamental material types used in current advanced production IC packages, the basic chemistries of the materials, the mechanical, thermal and electrical properties that make them desirable in different packaging applications, and the techniques that are used to fully characterize the materials’ applicability.  Lessons on material compatibility with high volume manufacturing will be shared.  Fundamental trade-offs and co-design decisions that must be made for first pass success will be described, and a full package development process will be encouraged.

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SSIA Members: S$1,350 nett per pax
Non-Members: S$1,800 nett per pax

The following critical materials applications will be covered:

  • Material Fundamentals: Fundamental mechanical, thermal and electrical characteristics of materials.
  • Molding Compounds: Molding compounds are major components of IC packages. Their basic chemistry, the role of different mold compound constituents such as fillers, mold release agents, processes vs. material characteristic trade-offs, voids, compaction, mold flash, cure characteristics, and warpage will be explained.  Critical adhesion requirements and adhesion test methods will be described.
  • Wire Bonds: Au and Cu wires are critical to interconnection in wire-bonded devices.
  • Substrates: Substrate materials are undergoing radical changes as thinner and thinner packages with tighter interconnect pitches require ever improved warpage characteristics. Substrate material composition, the importance of the number of glass layers, glass types, and interaction with via processes will be highlighted.
  • Plating and Surface Finishes: To most, the Cu plating of a substrate seems of little importance, but the characteristics of the plating can have a major impact on the reliability of the solder joints. Plating techniques to switch off voiding at the Cu/solder interface will be highlighted.
  • Solders: Solders form the main interconnect between area array packages and the system level PCB. The major solder alloys will be described, along with various expressions for representing the complex creep and plastic behavior over temperature and strain ranges.  The anisotropic character of Sn solders will be discussed, the impact of alloying additives highlighted, and measurement techniques for believable results will be described.
  • Thin Film Characterization: Integrated circuits achieve interconnection through a layered approach containing a variety of dielectric and metal layers. Thin film characterization techniques will be described for use during process development for optimal mechanical property selection.
  • Other Materials: Characteristics and property analysis of package materials such as build-up layers, solder masks, underfills, lead frame materials, under bump metals, polyimides and silicone coatings will be discussed.
  • Chip-Package Interaction: Chip-Package interaction is best address through thorough characterization of the die’s dielectric stack-up strength in interaction with package stresses.  Modeling and test structures, as well as a package development process to mitigate CPI risks will be taught.


  • Participants will have a thorough knowledge of IC Package Materials, their characteristics, measurement techniques, and manufacturability issues.
  • Participants will understand the trade-offs between material properties, reliability, processing complexity, and costs.
  • Participants will understand how environmental variables such as moisture can impact material properties, how properties can be different at the beginning and end of a lot’s lifetime, and how to account for these changes in the qualification of a package.
  • The interplay between package material choices and chip reliability, especially in this day of TSV’s and low-k dielectrics, will be understood.
  • Class participants will have a good understanding of co-design strategies and package development processes to enable on-time qualification of new package builds of materials.


This course is designed for Packaging Engineer, Process Engineer, FEA Engineer, Materials Engineer, Sub-Con Management Engineer, Quality Control Engineer, Reliability Engineer and Failure Analysis Engineer.


The experience and knowledge sharing by the trainer will help establish high level of knowledge transfer/skill building to the audience in shortest time.


1. Motivation and Package Drivers

    • Material Selection Nightmares
    • Package Materials: Past, Present, Future

2. Material Characteristics

    • Mechanical
    • Thermal
    • Electrical

3. Materials Measurement Techniques

    • TMA, TGA, DMA
    • Fracture Toughness
    • Adhesion Characterization Methods
    • Thermal and Electrical Characterization Methods
    • Thin Film Characterization Methods

4. Fundamental Package Materials

  • Mold Compounds
  • Die Attaches
  • Wire Bond Materials
  • Underfills
  • Substrates
  • Plated Metals
  • Solders
  • Build-up materials
  • Solder Masks
  • Lead Frames
  • Die Coatings
  • Under-bump Metallurgies

5. Material Selection

    • Package Development Strategy
    • Co-Design
    • Package Test Structures
    • Qualification By Similarity

6. Case Studies and Q&A session


Mr. Darvin Edwards

B.S. Physics

Passport number : 536492643 ( For PSMB reference)

Darvin R. Edwards received the B.S. degree in Physics from Arizona State University, Tempe, AZ, in 1980 and joined Texas Instruments.

Elected TI Fellow in 1999, he was manager of the Advanced Package Modeling and Characterization group from 1997 through 2012.

In 2013, Darvin took responsibility for Analog Chip/Package Codesign, developing innovative test structures and design guidelines for TI’s new analog process nodes, including those of high voltage components.

Darvin is a two time past chair of the SRC GRC Interconnect and Packaging Sciences’ Science Area Coordinating Committee, and was TI’s IPS SAC and TAB representative for eight years.  He served as a liaison on a number of SRC research projects, working regularly with various universities and research institutes to coordinate TI’s external packaging research interests.

Professional activities have included over 30 years of service on the Applied Reliability program selection committee of the ECTC.  He has chaired this committee numerous times.  Within JEDEC, Darvin has authored five standards including the PCB specifications for low and high effective thermal conductivity test cards.   He has contributed to both the ITRS and iNEMI roadmaps.  He has authored and co-authored over 60 papers and articles in the field of IC packaging including two best paper awards and an Intel best student paper award, has written two book chapters, and has given multiple keynote addresses, lectures, tutorials, and short courses.  He holds 22 US patents.  Darvin is an IEEE Senior Member and is serving his fourth term on the CPMT Board of Governors.

We look forward to your participation.