EOS, ESD Issues In Manufacturing

Electrical Overstress (EOS) and Electrostatic Discharge (ESD) account for most of the field failures observed in the electronics industry. Although EOS and ESD damage can at times look quite similar to each other, the source each and the solution can be quite different. Therefore, it is important to be able to distinguish between the two mechanisms. The semiconductor industry needs knowledgeable engineers and scientists to understand these issues. EOS, ESD Issues in Manufacturing is a 2-day course that offers detailed instruction on EOS, ESD and how to distinguish between them. This course is designed for every manager, engineer, and technician concerned with EOS, ESD, analyzing field returns, determining impact, and developing mitigation techniques.

Participants learn to develop the skills to determine what constitutes a good ESD design, how to recognize devices that can reduce ESD susceptibility, and how to design new ESD structures for a variety of technologies include latest Cu Pillar, TSV and FinFET technologies.

  • Overview of the EOS Failure Mechanism. Participants learn the fundamentals of EOS, the physics behind overstress conditions, test equipment, sources of EOS, and the results of failure.
  • Overview of the ESD Failure Mechanism. Participants learn the fundamentals of ESD, the physics behind overstress conditions, test equipment, test protocols, and the results of failure.
  • ESD Circuit Design Issues. Participants learn how designers develop circuits to protect against ESD damage. This includes MOSFETs, diodes, off-chip driver circuits, receiver circuits, and power clamps.
  • How to Differentiate. Participants learn how to tell the difference between EOS and ESD. They learn how to simulate damage and interpret pulse widths, amplitudes and polarity.
  • Resolving EOS/ESD on the Manufacturing Floor. Participants see a number of common problems and their origins.

Please register your interest for the event by
dropping an email to daphne@ssia.org.sg


SSIA Members: S$1,350 nett per pax
Non-Members: S$1,800 nett per pax


  • The seminar will provide participants with an in-depth understanding of electrical overstress, the models used for EOS, and the manifestation of the mechanism.
  • Participants will understand the ESD failure mechanism, test structures, equipment, and testing methods used to achieve robust ESD resistance in today’s components.
  • The seminar will identify the major issues associated with ESD, and explain how they occur, how they are modeled, and how they are mitigated.
  • Participants will be able to identify basic ESD structures and how they are used to help reduce ESD susceptibility on semiconductor devices.
  • Participants will be able to distinguish between EOS and ESD when performing a failure analysis.
  • Participants will be able to estimate a pulse width, pulse amplitude, and determine the polarity of an EOS or ESD event.
  • Participants will see examples of common problems that result in EOS and ESD in the manufacturing environment.


Engineers/Mangers from QA, FA, Process, Design and other department that need an latest and in-depth understanding, EOS and ESD, the manifestation of the mechanism, its test structures, testing methods, distinguish between EOS and ESD when performing a failure analysis. see examples of common problems that result in EOS and ESD in the manufacturing environment.


1. Introduction

    • Terms and Definitions
    • ESD Fundamentals
    • EOS Fundamentals
    • Electrical Overstress Device Physics
    • Sources of EOS
    • EOS Models
    • Electrothermal Physics
    • Electrostatic Discharge Device Physics
    • ESD Models
    • ESD Testing and Qualification
    • ESD Failure Criteria
    • Electrothermal Physics
    • Electrostatic Discharge Failure Models
    • Semiconductor Devices and ESD Models
    • Latchup
    • EOS Issues in Manufacturing
    • Charging Associated with Equipment
    • Testers
    • Automated Handling Equipment
    • Soldering Irons
    • Charge Board Events
    • Cable Discharge Events
    • Ground Loops/Faulty Wiring
    • Voltage Differentials due to High Current
      i. Event Detection

2. ESD Protection Methods

  • Semiconductor Process Methods
  • MOSFET Design
  • Diode Design
  • Off-Chip Drivers
  • Receiver Networks
  • Power Clamps

3. Differentiating Between EOS and ESD

  • EOS Manifestation
  • ESD Manifestation
  • Circuit considerations
  • Chip level
  • System level
  • Simulating ESD
  • Simulating EOS

4. EOS/ESD Design and Modeling Tools

  • Electrothermal Circuit Design
  • Electrothermal Device Design

5. EOS/ESD Failure Analysis

  • Methodology
  • Case Studies
  • QnA session, end of workshop


Dr. Jeffrey Gambino

B.S. Degree in Materials Science

Senior technical staff at International Business Machines (IBM Microelectronics); CMOS integration at IBM Semiconductor Research and Development Center. In the past 30 year +, he has been involved in the Research and Development of RF technology, DRAM, On-chip interconnect technology, CMOS image sensor, Chip-package interaction, Cu Pillar, WLCSP, Through-silicon vias, , 3D Integration and latest FinFET process technologies.

Dr. Gambino received his B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and his Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices. In 1992, he joined the DRAM development alliance at IBM’s Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15-mm DRAM products. In 1999, he joined IBM’s manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic technology, Cu Pillar, WLCSP, 3D Packaging and latest FinFET Process Technology. He has published over 90 technical papers and holds over 100 patents.

We look forward to your participation.