Failure Analysis and Reliability Challenges for Advanced Semiconductor Technologies

COURSE OVERVIEW

Electronics are continuously growing more intricate and are being integrated into ever more mission critical applications such as autonomous vehicles, avionics, and implantable devices that literally sustain patients’ lives. Failure of any electronic device in these applications can cost millions of dollars, as well as result in loss of life. Even in devices where failures are not life threatening, customers’ expectations place stringent demands on product requirements. No one wants a product to fail within its expected lifetime. Failures during qualifications can delay product launches; failures early in a product’s lifetime can result in warrantee costs that destroy profitability, and after-warrantee failures can sour a customer’s esteem for a company, ruining brand loyalty and destroying repeat business.

This class will teach engineers from all disciplines of electronics the fundamental package failure modes and mechanisms that lead to product failures. With a knowledge of the failure mechanisms and a good understanding of the contributing factors, students of this class will be well positioned to design out failures, leading to first pass product success. The training will show multiple examples of failure mechanisms and solutions taken from traditional and new package styles such as FC-BGAs, WCSPs, and the newest fan-out and through silicon via technologies. Throughout, the emphasis will be on using this information to eliminate future problems.

Please register your interest for the event by clicking below. Alternatively you can drop an email to delia@ssia.org.sg

COURSE FEES:

SSIA Members: S$1,350 nett per pax
Non-Members: S$1,800 nett per pax

The following critical topics will be covered:

  • Reliability Fundamentals: This section will cover the basics of failure modes vs. failure mechanisms, requirements for sample sizes, concepts such as confidence limits, the Weibull distribution as a means to identify contributions from different failure mechanisms as well as extrapolating to low ppm failure rates, and foundational parameters for determining and maintaining process control.
  • Failure Analysis Methods: If you can’t find the failure mechanisms during process development or qualification, you won’t know where to concentrate corrective actions. This section will review failure analysis flows to optimize fault isolation, as well as covering individual techniques such as Scanning Acoustic Microscopy (SAM), Time Domain Reflectometry (TDR), thermal emissions testing, both wet and dry decapsulation, ion milling, parallel lapping, cross sectioning, die-and-pry, shadow Moiré warpage measurements, and many more. New techniques that have proven valuable for Cu wire bond, Pb-free, green materials and embedded device FA will be highlighted.
  • Failure Mechanisms and Solutions by Package Type: This section makes up the bulk of the training. Failure mechanisms and the contributing factors for major package types will be described. For every failure mechanism, both appropriate failure analysis techniques and optimized solutions will be described. Packages covered will include PBGAs, FC-BGAs, leaded devices such as TQFPs, Non-leaded Quad Flat Packs (QFNs), Wafer Scale Packages (WCSPs), and the newest package technologies such as Fan-out Wafer Level CSPs (FO-CSPs), embedded technologies and Through Silicon Via (TSV) devices. Failure mechanisms highlighted will include ILD damage under bumps and wire bonds, Cu vs. Au wire bond sensitivities, problems associated with delamination in the package, solder joint reliability, and system level issues such as drop, bend and aging reliability. Issues with finishes, moisture, and environmental contamination will be described. Practical lessons learned will be shared to ensure the students won’t make the same mistakes that others have already solved. This is a solution-focused course, so process parameters, design techniques and material selections that eliminate the failures and improve reliability will be emphasized to ensure students can design in reliability and design out failures.
  • Adhesion Tests and Characterization: Many of the package reliability failure mechanisms encountered result from a loss of adhesion. Practical adhesion test techniques will be describe to enable early screening of materials.
  • Reliability Tests and Standards: Test procedures for accelerating failures will be covered. Both industry standard tests and new, more highly accelerated test methods will be discussed. The goal, as always, is to accelerate mechanisms that will be found in the field while not creating any new or artificial mechanisms.
  • Reliable Package Development Process: Recommendations for process development, risk analysis, and up-front characterization with test structures will be made to give the student a framework for developing new, highly reliable packages. Students will learn concepts such as design for reliability, co- design, and qualification by similarity advantages and pitfalls.

COURSE OBJECTIVE

  • Participants will know how to identify and solve reliability issues in both current and future package technologies, speeding time to market and increasing package development
  • Participants will understand good failure analysis procedures and techniques to eliminate “failure not found” and false failure findings. They will be able to help guide failure diagnostic journeys to give their companies a competitive advantage over
  • Participants will be able to properly analyze and interpret reliability data, having a good understanding of statistical significance and common reliability charts. They will know the variables to control to ensure their products remain
  • The described structured approach to risk elimination in new products will reduce wasted efforts, failed qualifications, field failures, and will result in faster time to
  • An intuitive understanding of the interplay between materials, stresses, environmental conditions and reliability will help the student solve real-world problems for years to come

WHO SHOULD ATTEND

Failure Analysts, Yield, and Reliability Analysis Engineer, Researcher, Process Engineer, Product Engineer, NPI, RnD, Development Engineer, Developer, and Vendor of Failure Analysis equipment

FAST SKILL BUILDING METHODOLOGY

The experience and knowledge shared by the trainer will help establish high level of knowledge transfer/skill building to the audience in shortest time.

COURSE OUTLINE

1. Motivation

    • Reliability Nightmares and Their Causes
    • Upfront Development vs. Band-aid approaches

2. Fundamentals of Reliability

    • Bathtub Curve
    • Acceleration Factors
    • Sample Sizes and Confidence Limits
    • The Weibull Distribution
    • Cp and Cpk
    • Trend Charts

3. Failure Analysis

    • Failure Flow for Fault Isolation
    • Non-Destructive Methods: SAM, X-ray, 3D-X-ray, Optical Inspection, Witness Marks
    • Destructive FA: Cross Sectioning, Polish, Ion Mill, FIB, TEM, EDX

4. Failure Mechanisms and Solutions by Package Type (a sampling)

  • Common Mechanisms: Scribe Seal Damage, Shear Stress Cracking, Finish Problems
  • FC-BGA: White Bumps, Bump Electromigration, Cu Pillar Reliability, Underfill Reliability, Substrate Failure Mechanisms (Trace Cracking, Via Cracking, Barrel Cracking, Cu Anodic Filament Shorts), Solder Joint Reliability (Temperature Cycling, Drop), Warpage Reliability Issues (Head-in-Pillow, Board Level Impact), Bend Test and Cratering, Black Pad
  • Molded & Leaded Package: Moisture Sensitivity, Wire Bond Reliability, Delamination, and Wire Bonds (Stitch, Pad), Cu vs. Al Wire Bond Reliability, Wire Sweep vs. C Black Issues
  • WLCSP: Solder Joint Reliability, To Underfill or Not?, Die Strength
  • Embedded Die / Molded WLP: Delamination, Trace Cracking, Board Level Reliability
  • TSV: Micro Bump Reliability, Delamination, Cu Pumping
  • LEDs: Delamination, Yellowing
  • MEMS: Specific Requirements, Specialized Tests

5. Adhesion Tests for Material Selection

6. Reliability Tests and Standards

  • JEDEC, IPC, Mil Std

 

7. Package Process Development

  • Materials Selection
  • Co-Design
  • Package Test Structures
  • Design Rules
  • Qualification By Similarity

 

8. Q&A Session, end of workshop

INSTRUCTOR PROFILE

Mr. Darvin Edwards

B.S. Physics

Darvin R. Edwards received the B.S. degree in Physics from Arizona State University, Tempe, AZ, in 1980 and joined Texas Instruments.

Elected TI Fellow in 1999, he was manager of the Advanced Package Modeling and Characterization group from 1997 through 2012.

In 2013, Darvin took responsibility for Analog Chip/Package Codesign, developing innovative test structures and design guidelines for TI’s new analog process nodes, including those of high voltage components.

Darvin is a two time past chair of the SRC GRC Interconnect and Packaging Sciences’ Science Area Coordinating Committee, and was TI’s IPS SAC and TAB representative for eight years.  He served as a liaison on a number of SRC research projects, working regularly with various universities and research institutes to coordinate TI’s external packaging research interests.

Professional activities have included over 30 years of service on the Applied Reliability program selection committee of the ECTC.  He has chaired this committee numerous times.  Within JEDEC, Darvin has authored five standards including the PCB specifications for low and high effective thermal conductivity test cards.   He has contributed to both the ITRS and iNEMI roadmaps.  He has authored and co-authored over 60 papers and articles in the field of IC packaging including two best paper awards and an Intel best student paper award, has written two book chapters, and has given multiple keynote addresses, lectures, tutorials, and short courses.  He holds 22 US patents.  Darvin is an IEEE Senior Member and is serving his fourth term on the CPMT Board of Governors.

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