FinFET Technology and Challenges

FinFET transistor architecture is fast becoming the technology of choice at feature sizes below 20nm. The FinFET Technology and Challenges course will explain FinFET technology and its semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.

Participants learn basic but powerful aspects about FinFET technology. This skill-building series is divided into three segments:.

  • FinFET Device Physics Overview. Participants study the device physics associated with the FinFET. They learn why the FinFET has better channel control and how that translates into better performance than a planar FET.
  • FinFET Manufacturing Overview. Participants learn how semiconductor manufacturers are currently processing FinFET devices and the difficulties associated with three-dimensional structures from a processing and metrology standpoint.
  • FinFET Reliability. They also study the failure mechanisms and techniques used for studying the reliability of these devices.

Please register your interest for the event by
dropping an email to daphne@ssia.org.sg

COURSE FEES:

SSIA Members: S$1,350 nett per pax
Non-Members: S$1,800 nett per pax

COURSE OBJECTIVE

  • The seminar will provide participants with an indepth understanding of FinFET technology and the technical issues.
  • Participants will understand how these devices are manufactured and the various types of FinFETs.
  • Participants will understand the difficulties associated with non-planar structures and methods to alleviate the problems.
  • Participants will be able to make decisions about how to evaluate FinFET devices and what changes are likely to emerge in the coming years.
  • Participants will learn about FinFET Reliability and the failure modes associated with these devices.
  • Finally, the participants see a comparison between FD-SOI (the leading alternative) and FinFETs.

WHO SHOULD ATTEND

Process engineer, product engineer, NPI, RnD, Development engineer, Failure Analysts, Yield, and Reliability Analysis engineer, Researcher, Developer, and vendor of wafer fab equipment.

FAST SKILL BUILDING METHODOLOGY

The experience and knowledge sharing by the trainer will help establish high level of knowledge transfer/skill building to the audience in shortest time.

COURSE OUTLINE

1. Device Physics

    • Planar FET characteristics
    • FinFET characteristics
    • Performance comparisons

2. FinFET Manufacturing Overview

    • Substrates
      Bulk
      SOI
    • FinFET Types
    • Process Sequence
    • Processing Issues
      Lithography
      Etch
      Metrology

3. FinFET Reliability

  • Defect density issues
  • Gate Stack
  • Transistor Reliability (BTI and Hot Carriers)
  • Heat dissipation issues
  • Failure analysis challenges

4. Future Directions for FinFETs

  • Comparison of FD-SOI and FinFETs – Are FinFETs a better choice?
  • Scaling

5. Summary

6. Q&A session, End of class

INSTRUCTOR PROFILE

Dr. Jeffrey Gambino

B.S. Degree in Materials Science

Senior technical staff at International Business Machines (IBM Microelectronics); CMOS integration at IBM Semiconductor Research and Development Center. In the past 30 year +, he has been involved in the Researh and Development of RF technology, DRAM, On-chip interconnect technology, CMOS image sensor, Chip-package interaction, Cu Pillar, WLCSP, Through-silicon vias, , 3D Integration and latest FinFET process technologies.

Dr. Gambino received his B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and his Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices. In 1992, he joined the DRAM development alliance at IBM’s Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15-mm DRAM products. In 1999, he joined IBM’s manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic technology, Cu Pillar, WLCSP, 3D Packaging and latest FinFET Process Technology. He has published over 90 technical papers and holds over 100 patents.

We look forward to your participation.