Modern Nanoelectronics : From FinFET to Emerging Future Technologies

COURSE OVERVIEW

The CMOS transistor, the basis for our modern electronics word, has gone on a wild ride in the last 16 years, with unprecedented changes to both materials and architecture. Change started with the introduction of strain engineering at the 90 nm node. Subsequently at every other node a major device change has occurred: high-k/metal gate at the 45 nm node, and the FinFET device architecture at the 22 nm node. Each of these changes is important in the journey to the 14 nm node, but each carries hidden trade-offs and seriously complicates integration. The aim of this 2 day course is to understand the issues around modern nanoelectronics, which have arisen in the last 16 years of scaling, and which are partly but not fully addressed by these innovations. The participant will be given the tools to understand why these changes occurred, why they occurred when they did, and what the alternatives were. The course will focus on device design aspects, although integration issues will also be discussed. The course will start with a quick review of MOS device operation, with a focus on concepts necessary to understand modern device features, including scaling. After the preliminary concepts have been covered the journey to the 14 nm node will begin at the 120 nm node. This last classical node is a good starting point because with a polysilicon gate, silicon dioxide gate dielectric, and a bulk device architecture it represents the classical scaling regime that made electronics ever more powerful
from the 1960 to 2000. Then the course will then go on an in-depth chronological journey though the modern technology nodes in the historical order of introduction, covering strain engineering, high-k/ metal gate, and the FinFET device architecture. Each innovation will be described in detail, and critically evaluated to uncover its trade-offs and real benefits. Once arriving at the 14 nm node the course will have an in-depth look at the final (or current) product of electronic innovation: the strained, high-k/metal gate bulk FinFET device.

Please register your interest for the event by clicking below. Alternatively you can drop an email to delia@ssia.org.sg

COURSE FEES:

SSIA Members: S$1,350 nett per pax

Non-Members: S$1,800 nett per pax

COURSE OBJECTIVES

To provide a review of MOS transistor operation principles, with a focus on concepts required to understand device scaling to the 14 nm node. A simple subthreshold behavior model using capacitive division will be introduced and used throughout the course to analyze scaling options.
To provide an understanding of the issues and benefits of MOS channel strain engineering introduced at the 90 nm node.
To provide an understanding of the issues and benefits of high-k/metal gate integration introduced at the 45 nm node.
To provide an understanding of the issues and benefits of the FinFET device architecture introduced at the 22 nm node.
To provide an in depth look at the modern 14 nm bulk FinFET technology incorporating scaled strain, high-k/metal gate, and the 3D FinFET architecture on a highly scaled platform.

WHO SHOULD ATTEND

Engineers/Managers who require an in-depth understanding of CMOS device engineering down to the latest technology nodes. Some knowledge of transistor behavior and process integration is assumed in the course, however participants are encouraged to ask questions and seek clarification.

COURSE OUTLINE

1.Accelerated review/introduction to electronic devices:

Section will rapidly cover the fundamental physics underlying electron devices. Topics will include: electron statistics, semiconductor band structure, Fermi levels, and band diagrams.

2. Accelerated review/introduction to electronic devices:

Section will cover the behavior of Metal-OxideSemiconductor (MOS) capacitors, and long channel MetalOxide-Semiconductor-Field-Effect-Transistors (MOSFETs).

3. MOSFET Short-Channel Effects:

Section will cover the behavior and effects relating to sub-1um MOSFET effects.
Effects such as threshold voltage roll-off as a function of reducing gate-length, and drain induced barrier lowering (DIBL) will be covered.

4. MOSFET Metrics and characterization:

Section will cover the electrical metrics for modern transistors with a close look at the details of Vt-roll off plots, on-current targets, off-current targets, and Ion-Ioff plots.

5. Entering Nanoelectronics – 130nm node:

Section will cover the 130nm node focusing on Intel’s poly-Si gate device with a 1.5nm gate oxide. In some ways this node represents the last classically scaled node where gate oxide can be scaled geometrically, and it also represents the first nanoelectronics node where the gate lengths are <100nm. The major challenge to in scaling to the 130nm node and beyond was gate oxide tunneling current, which will also be covered in detail.

6. Nanoelectronics – 90nm node:

Section will cover the 90nm node focusing on strain engineering technique such as nitride stress liners and embedded Si-Ge epitaxy.

7. Naneleoctronics – 45nm node:

Section will cover the approaches to metal gate and high-k gate dielectric integration, with a focus on Intel’s 45nm metal-gate high-k process.
The metal gate / high-k technology

8.Nanoelectronics – 22nm node:

Section will cover alternative transistor structures such as SOI and FinFET. Discussion will start with traditional SOI, continue to double gate and multiple gate FinFETs, and end with a close look at the 22nm
technology from Intel featuring the triangular bulk FinFET design.

9. Nanoelectronics – 14 nm node:

Section will cover the state of the art bulk FinFET technology at the 14 nm node looking at the structure, issues and challenges. Detailed look at device and integration aspects, will be given and future challenges such as source/drain tunneling will be discussed.

10.Naneleoctronics – Future directions:

Section will cover my view on the future directions for CMOS logic nanotechnology, with a focus on low power and 3D integration. Topics covered will be super-subthreshold slope devices, lowpower optimized CMOS, sub-threshold logic, and 3D integration in logic and memory technologies.

11. Nanoelectroincs –Future directions:

Section will cover new and novel electronics materials that may have the potential to replace silicon transistors in the future. Carbon, in the form of carbon nanotubes and graphene sheets, is arguably the most promising material of the future and will be covered in detail.

12. Discussions:

Recap on concepts covered in the class, open discussion about technology trends and directions, question and answer session.

INSTRUCTOR PROFILE

Jakub Kedzierski

Ph.D. in electrical engineering

Jakub Kedzierski received his Ph.D. in electrical engineering from the University of California at Berkeley in 2001, where he co-invented the FinFET transistor, a device architecture currently used all over the world for deeply scaled technology nodes. Following his graduation he worked at IBM’s T. J. Watson Research Center on advanced silicon devices, continuing work on the FinFET and pioneering fully silicided metal gate technology. In 2005 he moved to MIT Lincoln Laboratory. At MIT, Jakub has led the work on low-power electronics, graphene transistors, and microfluidics. He designed an ultra-low power CMOS technology, built one of the world’s first top gated graphene transistors, and helped to initiate and grow the microfluidic research program in the Advanced Technology Division. He served as the assistant group leader in the Advanced Silicon Technology group, and as a visiting professor at the Indian Institute of Technology Bombay, in Mumbai (2012), where he taught courses on nanoelectronics and experimental design. Currently, Jakub is a Senior Scientist at MIT Lincoln Laboratory working on advanced microsystems. He has received both the IEEE EDS Paul Rappaport and IEEE George Smith Awards for best paper in 2001 and 2009 respectively. He has also received the best paper award from MIT Lincoln Laboratory for work in microhydraulics in 2016; he has over 60 publications.