Heterogeneous Packaging, SiP and Related Technologies and Future Challenges

COURSE OVERVIEW

Heterogeneous packaging is a natural outgrowth of hybrid and multi-chip packaging technologies which have developed to enable 5G telecommunication, autonomous vehicles, and Internet of Things (IoT) applications. Newly developed processes such as high- density interconnect substrates, Through Silicon Vias (TSVs), Fan-Out Wafer Level Packaging (FOWLP), integrated passives, and embedded antennas have made the promises of heterogeneous packaging, or System-in-a-Package (SiP), a reality. What are those promises? Better performance, higher circuit density for more compact electronics and easier system level design. With heterogeneous packaging, die with the best processes for a given functionality can be selected and integrated into a single system-in-a-package or module. For example, mixing analog and digital functions on a single die often results in performance compromises. With heterogeneous integration, the best analog, RF,  memory, and digital technologies can be combined for the ultimate in performance.

The recent technological developments that have empowered heterogeneous packaging will be covered in this class to give attendees a working knowledge that can be quickly applied. The class will also provide tools to enable each attendee to bring products to market faster. Firstly, high density redistribution layer (RDL) technologies and process flows will be described. Technologies to embed die directly in these substrates will be highlighted. Advantages of glass, organic, and Si substrate materials will be contrasted as related to both process complexity and high-speed signaling and RF. Next, novel packaging technologies that enable high-speed device stacking such as through silicon via etching, deep trench Cu plating, Back End of Line (BOEL) via first, via middle, and via last technologies, carrier wafer attach/detach, wafer thinning, micro bumping, chip-to-chip joining, and sili- con interposers will be detailed. Application of FOWLP technologies to help cost reduce heterogeneous modules will be presented covering chip-first and chip-last processes. Many high-density interconnect technologies allowing high-frequency antennas to be integrated onto the heterogeneous package substrates, basic concepts of embedded antennas and examples from industry will be presented.

Besides process technologies, this class will give insights into the thermomechanical, thermal, and electrical behavior of TSVs/FOWLPs and their reliability. It will show examples of TSV and FOWLP devices currently available in the marketplace and discuss future applications to mixed technology devices.

Finally, the current heterogeneous roadmap being developed under the auspices of the IEEE Electronic Packaging Society will be presented with a call for all interested parties to become involved in this important industry activity.

Please register your interest for the event by clicking below. Alternatively you can drop an email to delia@ssia.org.sg

COURSE FEES:

SSIA Members: S$1,350 nett per pax
Non-Members: S$1,800 nett per pax

The following critical topics will be covered:

  • Heterogeneous Packaging Evolution:Concepts from hybrid and multi-chip module history will be highlighted to give students an understanding of the rationale for the development of heterogeneous packaging to enable System-in-a-Package.
  • High Density Interconnect Substrate Technologies: Build-up interconnect technologies will be spotlighted to give students a working knowledge of the key concepts and technologies needed for heterogeneous package production. This section will include examples showing how ICs and passives can be embedded directly into substrates, especially those fabricated using Panel-Level-Packaging (PLP) technologies.
  • TSV Technologies: Fundamental process technologies such as deep via etching, Cu via plating, wafer polishing, micro bumping, chip-to-chip joining, underfilling, and chip attach will be emphasized. Different substrate choices, such as silicon vs. glass interposers will be discussed with an eye towards performance, reliability, and cost.
  • FOWLP Packaging and Reliability:The unit processes required for FOWLP, both mold- first and RDL-first will be examined, with a trade-off analysis for each one. Warpage is a primary concern for FOWLPs, so no discussion would be complete without detailing factors that impact package warpage and warpage measurement techniques. Reliability issues associated with FOWLP such as board level reliability (BLR) and trace integrity will be presented.
  • Embedded Antenna Basics: Basic antenna design concepts must be understood by those wishing to form fully heterogeneous packages for 5G technologies. Intuitive antenna theory will be provided, along with multiple examples of antenna types which can be applied in heterogeneous packages.

COURSE OBJECTIVES

  • Students will understand what is meant by heterogeneous integration, the advantages of these technologies, and how they can be used to rapidly develop modules to enable new product market introductions.
  • Students will have a working knowledge of high-density interconnect production techniques, performance, and trade-offs. Examples of current devices utilizing these technologies will help students understand how to extend those technologies to their own devices.
  • Participants will understand the fundamental TSV technologies and the trade-offs made between them. They will understand the strengths and weaknesses of TSVs applied to heterogeneous packages
  • Students will know the current state of Fan-Out Wafer Level Packaging, the process- es and materials used, and the fundamental reliability issues associated with these

WHO SHOULD ATTEND

Failure Analysts, Yield, and Reliability Analysis Engineer, Researcher, Process Engineer, Product Engineer, NPI, RnD, Development Engineer, Developer, and Vendor of Failure

FAST SKILL BUILDING METHODOLOGY

The experience and knowledge sharing by the trainer will help establish a high level of knowledge transfer/skill-building to the audience in the shortest time.

COURSE OUTLINE

1.The Heterogeneous Packaging Revolution

    • Why heterogeneous packaging?
      –Hybrid technologies
      -Multi-chip technologies
      -Heterogeneous technologies

2.High Density Interconnect Technologies

    • Build-up processes

      – Plating

    • Additive interconnect
      -Build-up materials
    • Electrical and mechanical characteristics
      -Substrate selection
      -Si, glass, organic

      -Electrical and process trade-offs

    • Active and passive embedding

3.Through Silicon Vias

    • Why Through Silicon Vias?

      -Strengths and weaknesses for heterogeneous integration

      Destructive FA: Cross Sectioning, Polish, Ion Mill, FIB, TEM, EDX

    • Current TSV Examples
    • Via Etching Technology
    • Via Plating Technology
    • Via First, Middle, vs. Last
    • Wafer Thinning and Carrier Wafers
    • Micro Bump Plating Technologies
    • Chip-to-Chip Bonding
    • Known-Good Die and Testing

4. TSV Reliability

  • Thermomechanical Stresses, Piezo-Resistive Effects, and Keep-Out Zones
  • Thermomechanical Stresses and Damage: Pumping, Dielectric Cracking, Silicon Cracking
  • Characterization

5.Fan-Out Wafer Level Package Technologies:

  • Thermomechanical Stresses, Piezo-Resistive Effects, and Keep-Out Zones
  • RDL-First Carrier Processes
  • Panel-Level-Package Processing
  • FOWLP Reliability
    -BLR vs. Die Size
    -Trace Integrity
    -Warpage

6.RF Integration

  • Transmission line theory basics
  • Antenna basics
  • Embedded antenna examples for heterogeneous integration

7.The Heterogeneous Packaging Roadmap

8.Q&A Session, end of workshop

INSTRUCTOR PROFILE

Mr. Darvin Edwards

B.S. Physics

Darvin R. Edwards received the B.S. degree in Physics from Arizona State University, Tempe, AZ, in 1980 and joined Texas Instruments soon after. Initially at TI, he developed integrated test structures such as strain gauges, moisture sensors, thermal sensors, and structures to determine the impact of package stresses on IC thin film layers. He developed a set of IC design rules for packaging that has been continuously updated and is still in use today. He then worked to build TI’s competence in thermal characterization and thermal management. He wrote a thermal characterization modeling program that was used within TI from 1993 through 2004 and built TI’s thermal labs. With JEDEC, he wrote the thermal test board standards. Elected TI Fellow in 1999, he was the manager of the Advanced Package Modeling and Characterization group from 1997 through 2012. His modeling team was responsible for thermal, electrical, and stress analysis for a wide range of product families, as well as ensuring reliability, successful qualification and introduction of products to the market. Packages and technologies he has helped develop include TSV, POP, Cu Pillar, Stacked Die, MCM, FC-BGA, PBGA, QFN, CSP, WLCSP, QFP, LOC, multi-die

QFP, and SOICs. In 2013, Darvin took responsibility for Analog Chip/Package Codesign, develop- ing innovative test structures and reliability design guidelines for TI’s new analog process nodes, including those of high voltage components. Additionally, he created and codified a risk assessment process that was implemented worldwide for TI’s new package development projects. During his career at TI, Darvin also managed at various times advanced package FA technique development, adhesion characterization development, and Sun Flip-Chip microprocessor package development. Darvin is a two time past chair of the SRC GRC Interconnect and Packaging Sciences’ Science Area Coordinating Committee, and was TI’s IPS SAC and TAB representative for eight years. He served as a liaison on a number of SRC research projects, working regularly with various universities and research institutes to coordinate TI’s external packaging research interests. Professional activities have included over 35 years of service on the Applied Reliability program selection committee of the ECTC. He has chaired this committee numerous times. Within JEDEC, Darvin has authored five standards including the PCB specifications for low and high effective thermal conductivity test cards. He has contributed to both the ITRS and iNEMI

roadmaps. He has authored and co-authored over 60 papers and articles in the field of IC packaging including two best paper awards and an Intel best student paper award, has written two book chapters, and has given multiple keynote addresses, lectures, tutorials, and short courses. He holds 22 US patents. Darvin is an IEEE Senior Member and is serving his fourth term on the CPMT Board of Governors.

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